1. Technical Field
Various embodiments relate to a semiconductor apparatus, and more particularly, to a bit line discharge circuit of a nonvolatile memory apparatus.
2. Related Art
A nonvolatile memory, in particular, a phase change RAM (PCRAM), which stores information using a phase change substance, is a nonvolatile memory apparatus which employs a phase change according to a temperature condition, that is, a resistance value change according to the phase change.
A phase change substance is a substance which can be changed into an amorphous state and a crystalline state according to a temperature condition. A typical phase change substance is a Chalcogenide alloy. Because a representative Chalcogenide alloy is Ge2Sb2Te5 (GST) which uses germanium (Ge), antimony (Sb) and tellurium (Te), a phase change substance is generally referred to as ‘GST’.
In the PCRAM, a reversible phase change between the crystalline state and the amorphous state of the phase change substance (GST) occurs using Joule heating which is induced by application of current or a voltage of a specific condition to the phase change substance (GST). The crystalline state is referred to as a set state in terms of a circuit. In the set state, the phase change substance (GST) has electrical characteristics of a metal with a low resistance value. Also, the amorphous state is referred to as a reset state in terms of a circuit. In the reset state, the phase change substance (GST) has a resistance value higher than that in the set state. That is to say, the PCRAM stores information using a resistance value change between the crystalline state and the amorphous state, and discriminates stored information by sensing current flowing through the phase change substance (GST) or a voltage variation according to current variation.
FIG. 1 is a block diagram of a conventional nonvolatile memory apparatus 1.
The nonvolatile memory apparatus 1 includes a sensing node level control unit 10, a write current driving unit 20, a sensing current driving unit 30, a sense amplifier 40, and a memory cell 50.
The write current driving unit 20 includes an NMOS transistor N. The memory cell 50 includes a phase change device R_GST which is constituted by a phase change substance, and a cell diode D1.
The sensing node level control unit 10 operates in response to a control signal CTR, compares a reference voltage VREF and the voltage of a sensing node SN, and outputs an enable signal EN. The control signal CTR is a signal which controls a read operation and a write operation of the nonvolatile memory apparatus 1. The control signal CTR drives the sensing node level control unit 10 in the write operation of the nonvolatile memory apparatus 1, and drives the sensing current driving unit 30 in the read operation of the nonvolatile memory apparatus 1.
The sensing node level control unit 10 operates in response to the control signal CTR in the write operation, is fed back with the voltage of the sensing node SN, and outputs the enable signal EN which can operate the write current driving unit 20. If the voltage level of the sensing node SN is lower than the voltage level of the reference voltage VREF, the enable signal EN is activated, and if the voltage level of the sensing node SN is higher than the voltage level of the reference voltage VREF, the enable signal EN is deactivated.
The NMOS transistor N of the write current driving unit 20 receives a first driving voltage VPP through a drain terminal D, and supplies write current I_WRITE through a source terminal S which is connected with a bit line BL, in response to the activated enable signal EN which is applied to a gate terminal G.
The memory cell 50 changes the resistance value of the phase change device R_GST when the write current I_WRITE is supplied in the direction of the ground voltage VSS.
Conversely, in the read operation of the nonvolatile memory apparatus 1, the sensing current driving unit 30 outputs sensing current I_SENSE to the memory cell 50 in response to the control signal CTR by using a second driving voltage VDD. The sense amplifier 40 senses the sensing current I_SENSE which varies according to the resistance value of the phase change substance R_GST and outputs data DQ. The sense amplifier 40 also receives a second reference voltage VREF2 through its positive terminal.
In general, the voltage level of the first driving voltage VPP supplied in the write operation of the nonvolatile memory apparatus 1 is higher than the voltage level of the second driving voltage VDD supplied in the read operation of the nonvolatile memory apparatus 1. This is to cause a phase change by inducing Joule heating in the phase change device R_GST in the write operation.
In this regard, even in the case where the enable signal EN is deactivated not to operate the NMOS transistor N of the write current driving unit 20, leakage current may be caused in the NMOS transistor N in the direction of the bit line BL by the first driving voltage VPP as a high voltage, due to gate-induced drain leakage (GIDL).
As a consequence, a problem may be encountered in that such leakage current influences the sensing current I_SENSE in the read operation and thus the data DQ stored in the memory cell 50 is likely to be erroneously read and outputted.